An area -efficient, high-performance, low-power multi-port cache memory architecture.
Item
-
Title
-
An area -efficient, high-performance, low-power multi-port cache memory architecture.
-
Identifier
-
AAI3283200
-
identifier
-
3283200
-
Creator
-
Bajwa, Hassan.
-
Contributor
-
Adviser: Xinghao Chen
-
Date
-
2007
-
Language
-
English
-
Publisher
-
City University of New York.
-
Subject
-
Engineering, Electronics and Electrical
-
Abstract
-
In recent years significant research activities have been geared toward reducing bottleneck caused by slow READ and WRITE operations of conventional memories. Ever increasing power-hungry applications and hardware have stretched present memory architecture and technology to the limit. Increasing cache sizes and the number of cache levels between microprocessors are no longer a practical solution as low cost as well as low access latency imposes a restriction on the growth of cache size. Dual-port memory technologies, implemented with explicit duplication of word and bit lines for each port, have been widely applied to multi-core processors in recent years. Since the silicon areas used by word and bit lines dominate entire memory area, duplicating the word and bit lines results in large silicon area and increases bitline discharge and power dissipation [1]. It is not uncommon to have dual-core processors or Systems-on-Chip (SOC) applications where memory occupy more then 50% of the chip area [2]. Recently, as technology scaled down in the sub-micron regime, power dissipation due to leakage energy has become an important consideration in high performance microprocessor design. Leakage power dissipation, usually proportional to chip area has emerged as a dominant source of energy consumption [3, 4].;We have proposed a dynamically configured area-efficient memory architecture that can improve the performance of a traditional hardwired dual-port memory without explicitly duplicating the word and bit lines for the second port. In other words, the dual-ports in our design share the word and bit lines used in the traditional hardwired single-port memory. The new area-efficient dual-port memory technology employs a dynamically configured isolation circuit to divide a conventional memory into two virtually isolated blocks, thus allowing dual-port accesses simultaneously. These two virtually isolated memory blocks work just like two conventional single-port memories. Since no word and bit lines are explicitly added for the second port, the silicon size of the hardwired dual-port memory can be reduced almost to half, while allowing less power consumption and access latency at the same time. The dynamic isolation of a memory block into two virtually isolated blocks is realized, utilizing the real time memory access addresses on the two ports.
-
Type
-
dissertation
-
Source
-
PQT Legacy CUNY.xlsx
-
degree
-
Ph.D.
