Performance analysis of a multistage packet-switched shared-memory multiprocessor system with restricted outstanding memory requests.
Item
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Title
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Performance analysis of a multistage packet-switched shared-memory multiprocessor system with restricted outstanding memory requests.
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Identifier
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AAI9618113
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identifier
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9618113
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Creator
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Wang, Chin Bin.
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Contributor
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Adviser: Theodore Brown
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Date
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1996
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Language
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English
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Publisher
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City University of New York.
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Subject
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Computer Science
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Abstract
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An approximation algorithm is designed for the performance analysis of a finite-buffered, packet-switched, asynchronous multistage multiprocessor system with restricted outstanding memory request. We first model the proposed machine by an open queuing network with restricted capacity. We then convert the open queuing network with restricted capacity into a corresponding closed queuing network and analyze the performance of this equivalent closed queuing network. Our algorithm is based on a decomposition method. We decompose the closed network into two sub-networks: sub1-network contains only a control node and sub2-network consists of the rest of nodes in the closed network. The sub2-network contains a finite number of stages through each of which messages are delivered successively in their transmissions. Blocking phenomena can occur on upstream paths preceding a full destination queue and the blocking effects of inter-stages are taken into account iteratively. The approximation algorithm for analyzing the performance of the sub2-network has two major steps: step 1 computes the performance of the network by backward procedure; step 2 computes the performance of the network by the forward procedure. Step 1 and step 2 are computed alternatively and repetitively until the difference of the performance measurement between step 1 and step 2 reach a small prescribed tolerance value. The throughput obtained from the sub2-network is considered to be the arrival rate entering the sub1-network. Then we aggregate the two sub-networks to derive the average queue length, average waiting time and average server utilization of the proposed machine. We verify the accuracy of our approximate algorithm by comparing to the result of simulation method. Our verifications show that our approximate algorithm is fairly good. Scale relationships for the various performance measurements affected by a number of parameters: the number of processors, the characteristic of processors, the number of memory modules, the characteristics of memory, the topology and characteristics of the interconnection network are developed and studied. Furthermore, we compare the performance when restricting each processor to a maximum number of outstanding memory requests to the performance when without restricting.
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Type
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dissertation
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Source
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PQT Legacy CUNY.xlsx
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degree
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Ph.D.
