Technology mapping algorithms of sequential circuits using LUT-based FPGAs.
Item
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Title
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Technology mapping algorithms of sequential circuits using LUT-based FPGAs.
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Identifier
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AAI9630522
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identifier
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9630522
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Creator
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Xu, Quan.
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Contributor
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Adviser: Stanley Habib
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Date
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1996
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Language
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English
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Publisher
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City University of New York.
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Subject
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Computer Science | Engineering, Electronics and Electrical
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Abstract
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This thesis explores the optimization of technology mapping of sequential circuits using look-up table based field programmable gate arrays (LUT-based FPGAs). The thesis first gives a brief survey of programmable logic devices and field programmable gate arrays, including their architectures in addition to previous research performed on technology mapping of look-up table based FPGAs. The thesis defines terminology used for sequential circuits. A concept of bell structure is defined and illustrated in the thesis. A sequential circuit can be represented as a bell network. Each bell consists of a hook, which is a series of flip-flops or a primary output node, and a cone of combinational logic units. A bell may be followed by another bell. A path from the top node of a cone to its following bell is defined as a joint. A joint and its following bell is then called a bell-bottom. Combinational logic units in different bells are disjoint. An technology mapping algorithm can then be applied to the combinational logic units in each bell. The thesis presents two groups of technology mapping algorithms for sequential circuits using LUT-based FPGAs. The first group of mapping algorithms, Hook Map, concentrates itself on hooks and their adjacent parts, that is, flip-flops and their adjacent combinational logic units. Analysis and evaluations of hook mapping are illustrated in the thesis. On the other hand, mapping of a joint, a cluster of combinational logic units between two hooks, is discussed in the second groups of technology mapping algorithms, Joint Map. Examples using the two groups of mapping algorithms show that these algorithms work better than some of existing algorithms. The research in this thesis also shows that optimal technology mapping algorithms for combinational function circuits may not be optimal for sequential circuits.
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Type
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dissertation
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Source
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PQT Legacy CUNY.xlsx
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degree
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Ph.D.
